ASIC/FPGA Design and Verification Out Source Services
The code for the master is not free.
The verilog code was tested with my free SD slave code, which is available on this site, as well as with some specman code from other customers. Some of the benefits available by the master code are:
- A new version of the code exists. The ROM xilinx components are replaced by
Samsung flash (k9f1208).
link
- A collection of verilog tasks, which enables easy creation of SD master simple transactions as well complex scenarios.
- Example of SD master initial scenario:"SD Initialization Code Description".
Both the RTL design and the test are also available in VHDL format.
The VHDL format is not free. For more information, send an e mail with
SD VHDL in the subject.
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