ASIC/FPGA  Design and Verification Out Source Services 
                            FFT data in store header
                            
//
//
//
//Data in goes to either one of two dual port RAMs.
//When the data to RAM stroe is ended, a flag is set. The flag is than
//reset when all of the data is read.
#include "systemc.h"
struct di: sc_module {
  //Input data store into one of two dual port RAM devices
  sc_in        di_v;//one cycle pulse for 16 samples
  sc_in >  din;
  //write port 
  sc_out >  addraq;
  sc_out weaq;       
  //write port B
  sc_out webq;       
  sc_out > diq;
  //
  //data out address
  sc_out >  addroq;
  //data out select
  sc_out      seloaq;
  sc_in        rst; //reset
  sc_in_clk CLK;
  //////////////////////////////////////////////
  sc_signal       addincq;
  sc_signal       addinci;
  sc_signal >  addrai;
  sc_signal       weai;
  sc_signal       webi;
  sc_signal >  addroi;
  sc_signal       start_rdq;
  sc_signal       start_rdi;
  sc_signal       seloai;
  SC_CTOR(di) {
    SC_METHOD(samp);
    sensitive << CLK.pos();
    SC_METHOD(addinc_p);
    sensitive << di_v << addraq;
    SC_METHOD(addra_p);
    sensitive << addincq << addraq;
    SC_METHOD(wea_p);
    sensitive << di_v << weaq << addraq;
    SC_METHOD(web_p);
    sensitive << di_v << weaq << addraq;
    SC_METHOD(addro_p);
    sensitive << addroq << start_rdq;
    SC_METHOD(start_rd_p);
    sensitive << addraq;
    SC_METHOD(seloa_p);
    sensitive << addroq << seloaq;
  }
  void samp();
  void addinc_p();
  void addra_p();
  void wea_p();
  void web_p();
  void addro_p();
  void start_rd_p();
  void seloa_p();
};
                             
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