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Dual Port RAM model in system C.

1. The following is a model for dual port RAM .
2. The read is asynchronous and the write is synchronous.
3. A test-bench with a generator is also included.
4. The test-bench generates VCD waves. It demonstrates the read update following write transaction.
5. People who were interested in this site also wanted to see the page regarding complex multiplier. ...Usually such a design uses four multipliers. This design does it with only three multipliers... press here for complex Multiplier, but the best way to navigate and look around things in my site is to use the search my site option.
6. The code is in the download area. Look for the file SCdpram.tar.gz.
   
7. The same functional memory, but with modular writing style, can be downloaded from: Look for the file SCdpramM.tar.gz.
   The code can be directly downloaded from: code of SCdpram.tar.gz
   
   

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My First sysremC program FCS c code for calculating CRC for ETHERNET Simple multiplier and a test-bench. A simple c-code program to read a memory array from verilog RTL, using VPI.

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