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SD to flash - a word about timing.

1. The following page discusses some considerations of timing in the SD to flash project.


2. The SD slave clock is 25 MHz. The flash has an asynchronous interface. The flash timing resolution is such that a 150 MHz on the flash side is a good choice.


3. The timing estimation, from xilinx, XST tool indicates that the design is going to meet the timing requirements:
   

Timing constraint: Default period analysis for Clock 'fl_clk'
  Clock period: 4.855ns (frequency: 205.986MHz)
  Total number of paths / destination ports: 3822 / 1160
-------------------------------------------------------------------------
Delay: 4.855ns (Levels of Logic = 5)
  Source: u_mem/u_wrt/u_slv_wff/DPRAq_3 (FF)
  Destination: u_mem/u_wrt/u_slv_wff/ffouq_3 (FF)
  Source Clock: fl_clk rising
  Destination Clock: fl_clk rising
...



4. Some of the flash commands require long delay to finish. So if erase command, for instance, will finish in 10 us, it is certainly acceptable to break some of the combinatorial logic involved, to improve timing. An example follows.
   The flash uses a very large finite state machine. Decoding the current state machine is done often and therefor has a gate count plus timing price. Decoding the next state has even a greater price. Having a register on each decode expression helps.

  signal c_read0q : std_logic;
  signal c_read0i : std_logic;
  signal c_cle_0q : std_logic;
  signal c_cle_0i : std_logic;
...
    else
      if(c_wbmb1q = '1' and c_read0q = '1') then
        was_stopi <= '0';
      elsif(c_cle_0q = '1') then --any a flash transaction start
        was_stopi <= '0';
      else
        was_stopi <= was_stopq;
      end if;
    end if;
  end process;
  c_read0i <= '1' when fsm_ns = C_READ0 else '0';
  c_wbmb1i <= '1' when fsm_ps = C_WBMB1 else '0';
  c_cle_0i <= '1' when fsm_ps = C_CLE_0 else '0';
...
  p_1 : process(clk, rst)
  begin
    if(rst = '1') then
...
      c_read0q <= c_read0i;

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