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Verilog enumerating example

// synthesis translate_off
wire [10*8:1] dbg_cs;
assign dbg_cs=
(c_state == CS_IDLE ) ? "CS_IDLE" :
(c_state == CS_RDEAY) ? "CS_RDEAY" :
(c_state == CS_IDENT) ? "CS_IDENT" :
(c_state == CS_STBY ) ? "CS_STBY" :
(c_state == CS_TRAN ) ? "CS_TRAN" :
(c_state == CS_DATA ) ? "CS_DATA" :
(c_state == CS_RCV ) ? "CS_RCV" :
(c_state == CS_PRG ) ? "CS_PRG" :
(c_state == CS_DIS ) ? "CS_DIS" :
"XX_XXXX";
// synthesis translate_on

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