ASIC/FPGA Design and Verification Out Source Services

Displaying State Machine Data With ASCII

1. VHDL supports enumerating enumerating example and type variables. This allow better readability and allow the simulator to show the values with their ASCII meaningfully names on wave to help debug process.
2. The following will show to do it with verilog and GTK wave viewer version v3.1.8(w)999-2008 BSI.
3. First you have to add some non-synthesis able code and telling your synthesizer to ignore it enumerating code .
4. The result is as nice and helpful as show below:


5. Based on this free verilg SD version, a non free VHDL SD project was created. It supports more SD commands like read burst, has a better test-bench and a set of bash scripts to automate and randomize the input stimuli. The VHDL implementation uses Samsung flash (k9f1208).

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