ASIC/FPGA Design and Verification Out Source Services

specman - example of back pressure temporal check.

This is a checker, that checks if a valid signal is de-asserted no more than one cycle after a DUT signal, namely xoff, is asserted. Then the check goes on and checks that as long as xoff is asserted, the valid is not asserted.
Note that if the test stops on DUT error, it also prints the time of the xoff assertion start, to help in debug.

back_pressure_tcm() @sigdin.clk_r is {
  while(TRUE) {
    wait true(sigdin.xoff_sig$ == 1);
    var bp_start_time : time = sys.time;
    wait [1]; --one cycle wait before start check ecery cycle
    first of {--till end of xoff
      {wait fall(sigdin.xoff_sig$);};--stop check
      {--of 2
         if(sigdin.valid_sig$ == 1) then {--check
           dut_error(
             "back pressure valid_sig is asserted while back pressure started on time ",
             bp_start_time
           );
         };
         wait;
      };--of 2
    };--first of
  };
};--back_pressure_tcm





If valid signal can be defined as an event, the code can be written in a simple expect statement:

event xoff_inp_L_ev is fall(sigdin.xoff_in$ ) @sigdin.clk_r;
event valid_o_H_ev  is rise(sigdou.valid_o$ ) @sigdin.clk_r;

  --debug
  --register the time of temporal expression start
  --print it in case of failure
  xoff_inp_L_time : time;
  on xoff_inp_L_ev {
    xoff_inp_L_time=sys.time;
  };
  on valid_o_H_ev {
    message(NONE, "valid_o_H_ev debug"); --reduce priority of this message, once all works well
  };
  --
  expect uart is @xoff_inp_L_ev => {[..2]; @valid_o_H_ev} @sigdin.clk_r
  else dut_error("uart did not assert valid for more than 2 clocks after xoff_in de-assert at ", xoff_inp_L_time);

Home	For a VHDL simple UART DUT, I created a small verification eVC. VHDL function, which generates random numbers.