ASIC/FPGA Design and Verification Out Source Services

This document presents a script, that generates a specman portmap from a VHDL file.

1. I just needed today to create a port map from a VHDL interface. Since there was many signals involved, I needed a script.


2. The script is invoked by:
   perl /home/pini/bin/signal_map.pl i8051_all.vhd


3. The result is :
   
   
   clk: out simple_port of bit is instance;
   keep bind(clk, external);
   keep clk.hdl_path() == "clk";
   
   xrm_wr: in simple_port of bit is instance;
   keep bind(xrm_wr, external);
   keep xrm_wr.hdl_path() == "xrm_wr";
   
4. Note for a vector the script uses uint with right number of bits.


5. The script is located at: port map script.

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