ASIC/FPGA Design and Verification Out Source Services

The following will describe the input bits to the CRC7 module. Three cases will be shown:

1. Please note that a newer version of the SD slave exists. It supports Samsung (k9f1208) flash instead of xilinx ROM. link to newer version



2. CRC7 calculation for a 48 bits command.
3. CRC7 calculation for a 48 bits response.
4. CRC7 calculation for a 136 bits response.

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CRC7 VCD Wave Description SDIO VCD CRC7 Wave Flow Last Release of VCD

SDIO Slave Free Code SD Card Status

For case 1 and 2 the CRC7 is calculated on 40 bits starting from the very first bit - the start bit. For case 3 the first two bits (start and transmission bits) and the six reserved ones, which follow, are skipped. Than 120 bits are fed to the CRC7 module.
In the following waveform a command with 48 bits is the input to the CRC7. The slave module needs to calculate the CRC7 and compare it to what is received from the line. Note the command starts with bits 2'b01.

The case of response with 48 bits is similar. The slave needs to calculate the CRC7 and add it to its response. Note the response starts with bits 2'b00.


Last the case of a response of 136 bits is shown. The slave needs to calculate the CRC7 and add it to its response. Note the response starts with bits 2'b00.


The entire simulation with the above signals as well as others, in VCD format, can be download from the download area at (LAST_REL.vcd.gz)

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