ASIC/FPGA Design and Verification Out Source Services

Displaying State Machine Data With ASCII.

VHDL supports enumerating (enumerating example) and type variables. This allow better readability and allow the simulator to show the values with their ASCII meaningfully names on wave to help debug process. The following will show to do it with verilog and GTK wave viewer version v3.1.8(w)999-2008 BSI. First you have to add some non-synthesis able code and telling your synthesizer to ignore it (enumerating example). The result is as nice and helpful as shown below:

Home	Download Area All about printing the instance name from a VHDL component. VHDL function, which generates random numbers.