ASIC/FPGA Design and Verification Out Source Services

Open Issues for SD Slave Free Code

1. The design does not support free of error read response for bus width of 1. I started to decode a separate counter for that. For 4 bits transaction the address advances on each transaction and therefor it works fine.
2. SD registers are not implemented and most values are answered by driving some constants.
3. Randomization checks to exercise the CRC calculation and timing were not done.
4. Write transactions are not supported.
5. General review of spec needs versus what is currently supported.


6. Please note, that a new version of the SD project is available on this site. It was converted to VHDL. It has a greater support for SD spec. It has a better test bench and a set of scripts, which allow random stimuli and automate the check. SD slave with Samsung flash (k9f1208) (vhdl project).

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