ASIC/FPGA Design and Verification Out Source Services

Digital Design
Complex Multiplier
Data Path and Control
Verbal Description

1. The first part of the data path performs one addition and multiplication.
2. The second part does addition only.
3. The outputs of the design are registered.
4. The output of the multiplier is registered as well. Multipliers are usually slow devices and therefor it is recommended to register their output.
5. The control is simple. It generates clock enable to the assorted registers.

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