ASIC/FPGA Design and Verification Out Source Services

Digital Design
A synchronous design with a single clock domain

1. The more portable (port your digital design from one vendor to another) your design is, the more cost reduction you can achieve.
2. A synchronous design, with a single clock domain, is key issue in facilitating static timing analysis by enabling the designer to focus on functional issues rather than on timing ones.
3. For a design with a single clock domain, STA results are obtainable by merely declaring this one clock frequency and setting the constraints for primary inputs and outputs.
4. For synchronous designs with multiple clock domains, special care must be taken in the handling of signals which cross domains:
   Synchronization registers should always be employed.
   Special nomenclature, to allow automatic switch (by means of scripts) between simulation and synthesis models, as well as an easy way to track down synchronizers in the net-list.
5. Some FPGA devices uses a DLL or PLL to achieve a more reliable clock distribution scheme by reducing clock skew.
6. DLL devices also help in reducing clock to output, which is the time it takes to transmit a signal from one chip to the next.

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