ASIC/FPGA Design and Verification Out Source Services

Digital Design
Synthesis General Flow

1. Common methods of synthesis include: top down and bottom up.
2. In top down, the synthesizer goes recursively and searches all modules and applies the user specified constraints. This method facilitates the effort of writing the synthesis control scripts, but requires more CPU memory during the synthesis process.
3. For very large designs, memory consumption and CPU run time becomes an issue affecting the entire process and a bottom up method may be preferred. It requires more work from the user to get all the design synthesized, but per each single synthesis run, less memory is used by the synthesis computer.

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