ASIC/FPGA Design and Verification Out Source Services

memory HDL models

This page has links to some memory VHDL models, which I used for simulations.

1. An asynchronous, written in VHDL, sparse memory model to reduce memory consumption: async vhdl memory


2. A synchronous write sparse memory model. The read is asynchronous. This model is very poplar with most FPGA devices. sync vhdl memory


3. A synchronous write sparse memory model, written in VPI - C-Programming interface to the Verilog HDL. sync VPI memory


4. The sparse memory model is also intensively used in post NGD simulation: how to simulate a post NGD verilog net-list


5. A sparse model for systemc can be found at: APB slave DUT and test-bench written in system c


6. A sparse model for for VHDL design, build in c code and Glib at: A memory model, for VHDL design, build in c code and Glib.






7. Also avialable on this site (non free): An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.

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